The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device manufactured by photolithography processing, a mask for exposure that is used in a photolithography step and a pattern correcting method.
Over the recent years, a device pattern having an extremely small size has been required to be formed on a semiconductor substrate in order to meet demands for speed-up and a higher density of the semiconductor device.
Submicronization of the semiconductor device is actualized by shortening a wavelength of a light source of an exposure apparatus employed for optical lithography. At the present, a design rule of the semiconductor device reaches a level that is equal to or less than 100 nm. This value is smaller than the wavelength of the light source of the exposure apparatus needed for transferring a mask pattern in an optical lithography step. For instance, a wavelength of an argon fluoride (ArF) excimer laser employed as the light source is on the order of 193 nm.
In this case, on the occasion of transferring the pattern on the mask onto the substrate by the optical lithography, the size of the pattern to be transferred exceeds a resolution limit. Therefore, an influence of an optical proximity effect due to diffraction etc augments, then a shape of the pattern formed on the substrate changes, and there occurs a difference between the size of the pattern that should be transferred from the mask pattern and the size of the pattern actually transferred onto the substrate. Such being the case, an optical proximity correction (OPC) method is proposed as a means for correcting this difference.
The OPC is a pattern transferring technology of correcting changes of the shape and the size of the pattern transferred onto the substrate by a method such as partially changing (making thicker or thinner) the mask pattern beforehand conversely to a (an actual) change of the pattern (the pattern gets thinner or thicker), which occurs when transferring the mask pattern onto the substrate, or a method of disposing a dummy pattern and so forth.
An example of the OPC will be explained with reference to FIGS. 1A, 1B, 2A and 2 B. FIGS. 1A and 2A respectively illustrate mask patterns on reticles (R1, R2). Further, FIGS. 1B and 2B respectively depict patterns formed by transferring the mask patterns on the reticles R1, R2 onto semiconductor substrates (W1, W2). Note that the semiconductor substrate is also referred to as a wafer.
For example, FIG. 1A shows a mask pattern 1 in which patterns are arrayed, and FIG. 1B illustrates a pattern 2 transferred onto the substrate by use of the mask pattern 1. In this example, the mask pattern is a pattern in which a multiplicity of rectangles is arrayed.
The mask pattern 1 in FIG. 1A includes a hatching area defined as a light shielding area and outlined regions defined as light transmitting regions. A transfer pattern 2 is formed onto the resist on the substrate by the light traveling through the light transmitting regions. In the array of the rectangles configuring the mask pattern 1, the optical proximity effect differs with respect to patterns 3 arranged inwardly of the array (in positions toward the center from an outer peripheral area of the array) and with respect to patterns 4 arranged along the outer peripheral area of the array, and hence such a problem arises that the transfer patterns have difference in their sizes. The OPC is applied in order to correct this difference.
For instance, the patterns arranged in the vicinity of the peripheral area of the array of rectangles are set, as seen about patterns 7 in FIG. 2A, larger than the patterns 4 in FIG. 1A in order to eliminate the difference in size. As a result, there is no size difference of the transfer pattern transferred onto the substrate (8 in FIG. 2B). Thus, according to the OPC, a light quantity of the light transmitting region is adjusted by changing the mask pattern size, thereby controlling the size of the transfer pattern on the substrate.
On the other hand, a low dielectric constant material, which is a so-called a low-K film, is used for an inter-layer insulating film of wiring in order to attain speed-up of the high-density semiconductor substrate. This aims at reducing a wiring capacity by employing the low dielectric constant material and, as a result, attaining the speed-up of the wiring.
A material such as SiOC has hitherto been known as the low dielectric constant material. Further, recently a porous insulating film called porous silica (porous silica (silicon oxide)) is used for decreasing the dielectric constant. This type of insulating film has a small etching selection ratio with respect to the resist used for forming the transfer pattern, and therefore a film such as a silicon nitride film is employed as an etching mask, wherein etching is thus conducted.
This type of nitrogen-contained insulating film might be used for avoiding such a problem that the dielectric constant increases when the low-K film is exposed to an ashing gas in a resist removal step (ashing step). For others, the nitrogen-contained insulating film is used as an intermediate etching stopper layer for forming a dual Damascene structure or as a cap layer in a CMP (Chemical Mechanical Planarization) step. It should be noted that the dual Damascene structure connotes a Damascene structure including both of grooves and holes. Further, the Damascene structure represents a structure in which the wiring is embedded in the groove.
On the occasion of using Cu etc as a wiring material, the dual Damascene structure is employed. In the dual Damascene structure, a wiring pattern and hole patterns connecting the wiring pattern upwardly and downwardly, are simultaneously formed. A feature of the dual Damascene structure is that after simultaneously forming a hole pattern layer and a wiring pattern layer in which Cu is embedded, Cu is further embedded by a plating method and is thereafter planarized by CMP method. It is to be noted that patent document 1 given below is known in relation to the technology described above.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 2005-64226